02432naa a22003738i 4500 5320 5320 00005320 FR-PaOEC 20211006062617.0 a o d i cr || |||m|n|| 190601s2017 ||| o i|0| 0 eng d (FR-PaOEC) FR-PaOEC ES-MaONT Wang, Yu 3339 Reconfigurable processor for deep learning in autonomous vehicles / Yu Wang ... [el al.] Geneva : International Telecommunication Union, 2017. 13 p. texto (visual) isbdcontent electrónico isbdmedia recurso en línea rdacarrier The rapid growth of civilian vehicles has stimulated the development of advanced driver assistance systems (ADASs) to be equipped in-car. Real-time autonomous vision (RTAV) is an essential part of the overall system, and the emergence of deep learning methods has greatly improved the system quality, which also requires the processor to offer a computing speed of tera operations per second (TOPS) and a power consumption of no more than 30 W with programmability. This article gives an overview of the trends of RTAV algorithms and different hardware solutions, and proposes a development route for the reconfigurable RTAV accelerator. We propose our field programmable gate array (FPGA) based system Aristotle, together with an all-stack software-hardware co design workflow including compression, compilation, and customized hardware architecture. Evaluation shows that our FPGA system can realize real-time processing on modern RTAV algorithms with a higher efficiency than peer CPU and GPU platforms. Our outlook based on the ASIC-based system design and the ongoing implementation of next generation memory would target a 100 TOPS performance with around 20 W power. Tecnologías habilitadoras digitales 18 Science and Technology Liang, Shuang 3340 Yao, Song 3341 Shan, Yi 3342 Han, Song 3343 Peng, Jinzhang 3344 Luo, Hong 3345 4843 ITU Journal: ICT Discoveries Vol. 2018, no. 1, p. 9-21 2018:1<9 2616-8375 itu-ilibrary.org https://www.itu.int/dms_pub/itu-s/opb/journal/S-JOURNAL-ICTS.V1I1-2017-2-PDF-E.pdf Acceso al documento 0 pdf ART udc 0 0 0 3 1 6270 01 01 online 2019-09-12 0 1000020175569 2019-09-12 00:00:00 2019-09-12 ART pdf